| 1. | Serial vs parallel bus structures
串行对并行总线结构 |
| 2. | The data transfer capacity ( in bits per second ) of a bit - parallel bus
每条位并行总线上可传输数据的容量,用比特秒表示。 |
| 3. | M industrial automation systems and integration - multiprocessor control system for industrial machines - part 1 : parallel bus
工业自动化系统和集成.工业机械用多处理器控制系统 |
| 4. | It is provided with function of others computer system ' s communication through parallel bus , and the types of output dataclass are defined
系统采用并行数据通信总线实现与计算机系统通信的功能，并对通信的输出数据类型进行了定义。 |
| 5. | The hardware of the controller use the hierarchical and modular designing ideas . it adopt parallel bus structure and the functional module can be expanded freely by the parallel bus
机器人控制器硬件部分按照层次化、模块化的思想设计,采用并行总线结构,可以按照需求扩展各个功能模块。 |
| 6. | Via communication module , tesys model u can be connected with automation system conveniently through parallel bus , modbus or as - i bus etc . , offering the most accurate and real - time monitoring and control
利用通信模块， tesysu电动机起动器可以通过并行总线、 modbus总线和as - i总线等方便的与自动化系统相连，提供对设备最为实时和准确的监控； |
| 7. | The part of control card development mainly consists of the definition and completion of parallel bus inside the cards container , the assignation of address , the applications of gal devices and the program and debugging of eprom software
控制卡研制部分的主要内容包括并行机箱内总线的定义与控制，系统寻址空间分配， gal器件应用，控制卡eprom程序设计等。 |
| 8. | Using pxi such a standard parallel bus interface to replace the non - standard process control data communication interface and using the software platform labwindows / cvi designed to pxi bus modules and other virtual instrumentation to replace the different kinds of configuration software make communication interface and software platform integrated
用pxi这种标准的通用线接口取代该过程控制实验装置的数据通讯接口,用labwindows / cvi这种针对pxi总线模块仪器等虚拟仪器设计的软件开发平台取代其组态软件,提高了系统的精度及其稳定性和灵活性。 |
| 9. | In the process of designing hardware , the principal and subordinate structure is adopted : the principal cpu accomplishes the communication with the group host computer ; the subordinate cpus accomplish the communication with some command post computers and observe post computers ; the principal and subordinate cpus exchange data through parallel bus to realize the communication between the group host computer and its subordinate computers
在硬件系统设计中，采用了主从结构：主cpu完成与群主机通信，从cpu完成与各指挥所、观察所计算机通信，再通过主从cpu间并行总线的数据交换来完成群主机与其下属计算机的通信。 |
